1. Technical Field
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of fabricating the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts are being made to study and develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, the LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a perspective view illustrating a LCD device according to the related art.
Referring to FIG. 1, the LCD device 51 includes an array substrate, a color filter substrate and a liquid crystal layer between the two substrates.
The color filter substrate includes a black matrix 6, and red (R), green (G) and blue (B) color filter patterns 7a, 7b and 7c on a second substrate 5. A common electrode 9 is disposed on the color filter patterns 7a, 7b and 7c. 
The array substrate includes a gate line 14 and a data line 26 crossing each other on a first substrate 10 to define a pixel region P. A thin film transistor T is disposed near a crossing portion of the gate and data lines 14 and 26. A pixel electrode 32 is disposed in the pixel region P and connected to the thin film transistor T.
The array substrate is fabricated with five mask processes. A gate electrode and the gate line are formed in a first mask process. A semiconductor layer is formed in a second mask process. A data line and source and drain electrodes are formed in a third mask process. A passivation layer having a contact hole exposing the drain electrode is formed in a fourth mask process. A pixel electrode is formed in a fifth mask process.
Because the array substrate is fabricated with the five mask processes, fabrication time and product cost increase. To resolve this problem, a method of fabricating an array substrate with four mask processes is suggested.
FIG. 2 is a plan view illustrating an array substrate for an LCD device fabricated with four mask processes according to the related art.
Referring to FIG. 2, a gate line 62 and a data line 98 cross each other on a substrate to define a pixel region P. A gate pad 66 is disposed at one end of the gate line 62, and a data pad 99 is disposed at one end of the data line 98. A gate pad electrode GP is disposed on the gate pad 66, and a data pad electrode DP is disposed on the data pad 99.
A thin film transistor T is disposed near a crossing portion of the gate and data lines 62 and 98. The thin film transistor T includes a gate electrode 64, a first semiconductor layer 90a, and source and drain electrodes 94 and 96. A pixel electrode PXL is disposed in the pixel region P and contacts the drain electrode 96.
A storage electrode 86 overlaps the gate line 62. The storage electrode 86, the gate line 62 and a gate insulating layer therebetween form a storage capacitor Cst.
A second semiconductor layer 90b is disposed below the data line 98, and a third semiconductor layer 90c is disposed below the storage electrode 86.
A portion of an active layer 92a of the first semiconductor layer 90a is not covered by the gate electrode 64. The portion of the active layer 92a is exposed to light such as backlight, and thus a photo current is generated. This photo current becomes a leakage current in the thin film transistor T.
Further, because metal patterns such as the data line 98, the storage electrode 86 and the source and drain electrodes 94 and 96, and the semiconductor patterns such as the first to third semiconductor layers 90a to 90c are formed with the same mask process, intrinsic amorphous silicon layers of the semiconductor patterns protrudes outside the metal patterns. The protruded portion of the intrinsic amorphous silicon layer of the second semiconductor layer 90b is also exposed to light such as backlight, and thus a photo current is generated. This causes a coupling with the pixel electrode PXL, and wavy noise occurs when displaying images.
FIGS. 3A and 3B are cross-sectional views taken along lines II-II and V-V of FIG. 2, respectively.
Referring to FIGS. 3A to 3B, when the array substrate is fabricated with the four mask processes, first and second semiconductor layers 90a and 90b are formed below source and drain electrodes 94 and 96 and data line 98, respectively. A passivation layer PAS is on the source and drain electrodes 94 and 96.
The first semiconductor layer 90a includes an active layer 92a of intrinsic amorphous silicon and an ohmic contact layer 92b of impurity-doped amorphous silicon. The second semiconductor layer 90b includes an intrinsic amorphous silicon layer 70 and an impurity-doped amorphous silicon layer 72.
A portion of the active layer 92a is not covered by a gate electrode 64. The portion of the active layer 92a is exposed to light such as backlight, and thus a photo current is generated. This photo current becomes a leakage current in a thin film transistor T. When the leakage current is generated, a voltage charged in a pixel region P abnormally leaks through the thin film transistor T. Accordingly, characteristics of the thin film transistor T are degraded.
Further, the intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b protrudes outside the data line 98. When the protruded portion of the intrinsic amorphous silicon layer 70 is exposed to light such as backlight, it is repeatedly activated and inactivated, and thus a photo current is generated. The photo current is coupled with the signal on a pixel electrode PXL, and arrangement of liquid crystal molecules is abnormally distorted. Accordingly, a wavy noise occurs that wave-shaped thin lines are displayed in a screen of the LCD device.
A distance between the data line 98 and the pixel electrode is generally about 4.75 um in consideration of alignment error. The intrinsic amorphous silicon layer 70 of the second semiconductor layer 90b protrudes outside the data line 98 with about 1.7 um. In the related art, a distance D between the data line 98 and the pixel electrode PXL is about 6.45 um (=4.75 um+1.7 um) due to the protrusion of the intrinsic amorphous silicon layer 70. Accordingly, the pixel electrode PXL is far away from the data line 98, and a width W1 of a black matrix BM to shield the data line 98 and the distance D increases, thus aperture ratio is reduced.
The above problems relate to the four mask processes according to the related art.
FIGS. 4A to 4G, 5A to 5G and 6A to 6G are cross-sectional views, taken along II-II, III-III and IV-IV of FIG. 2, respectively, illustrating a method of fabricating an array substrate for an LCD device with four mask processes according to the related art.
Referring to FIGS. 4A, 5A and 6A, a metallic material is deposited on a substrate 60 having a pixel region P, a switching region S, a gate region G, a data region D and a storage region C. The metallic material layer is patterned with a first mask process to form a gate line 62, a gate pad 66 and a gate electrode 64.
Referring to FIGS. 4B, 5B and 6B, a gate insulating layer 68, an intrinsic amorphous silicon layer 70, an impurity-doped amorphous silicon layer 72 and a metallic material layer 74 are formed on the substrate 60 having the gate line 62. A photoresist layer 76 is formed on the metallic material layer 74. A second mask M is disposed over the photoresist layer 76. The second mask M has a transmitting portion B1, a blocking portion B2 and a semi-transmitting portion B3. The semi-transmitting portion B3 and the blocking portions B2 at both sides of the semi-transmitting portion B3 correspond to the switching region S. The blocking portion B2 corresponds to the storage region S. The blocking portion B2 corresponds to the data region D. The photoresist layer 76 is exposed to light using the second mask M.
Referring to FIGS. 4C, 5C and 6C, first to third photoresist patterns 78a to 78c are formed in the switching region S, the data region D and the storage region S, respectively. The metallic material layer 74, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 are etched using the first to third photoresist patterns 78a to 78c. 
Referring to FIGS. 4D, 5D and 6D, first to third metal patterns 80, 82 and 86 are formed below the first to third photoresist patterns 78a to 78c. First to third semiconductor layers 90a to 90c are formed below the first to third metal patterns 80, 82 and 86. An ashing process is performed for the first to third photoresist patterns 78a to 78c to remove a thinner portion of the first photoresist pattern 78a. By the ashing process, the sides of the first to third photoresist patterns 78a to 78c are also removed. The first to third metal patterns 80, 82 and 86 and the impurity-doped amorphous silicon layer 72 of the first to third semiconductor layers 90a to 90c are etched with the ashed first to third photoresist patterns 78a to 78c. 
Referring to FIGS. 4E, 5E and 6E, source and drain electrodes 94 and 96, a data line 98 and a data pad 99 are formed. The third metal pattern 86 is referred to as a storage electrode 86. The impurity-doped amorphous silicon layer of the first semiconductor layer 90a is referred to as an ohmic contact layer 92b, and the intrinsic amorphous silicon layer of the first semiconductor layer 90a is referred to as an active layer 92a. The storage electrode 86 forms a storage capacitor Cst with the gate line 62.
When the first to third metal patterns (80,82 and 86 of FIGS. 4D, 5D and 6D) and the first to third semiconductor layers (90a to 90c of FIGS. 4D, 5D and 6D) are etched using the first to third ashed photoresist patterns 78a to 78c, the active layer 92a is over-etched so that impurities do not remain on the active layer 92a. 
Referring to FIGS. 4F, 5F, and 6F, a passivation layer PAS is formed on the substrate 60 having the data line 98. The passivation layer PAS is patterned with a third mask process to form a drain contact hole CH1 exposing the drain electrode 96, a storage contact hole CH2 exposing the storage electrode 86, and a data pad contact hole CH4 exposing the data pad 99. Also, the passivation layer PAS and the gate insulating layer 68 are patterned with the third mask process to form a gate pad contact hole CH3 exposing the gate pad 66.
Referring to FIGS. 4G, 5G and 6G, a transparent conductive material is deposited on the passivation layer PAS and patterned with a fourth mask process to form a pixel electrode PXL, a gate pad electrode GP and a data pad electrode DP. The pixel electrode PXL contacts the drain electrode 96 through the drain contact hole CH1 and the storage electrode 86 through the storage contact hole CH2. The gate pad electrode GP contacts the gate pad 66 through the gate pad contact hole CH3, and the data pad electrode DP contacts the data pad 99 through the data pad contact hole CH4.
Through the above four mask processes, the array substrate is fabricated. As explained above, the intrinsic amorphous silicon layer of the second semiconductor layer protrudes outside the data line. Accordingly, wavy noise occurs and aperture ratio is reduced.
Further, the portion of the active layer is not covered by the gate electrode. Accordingly, the leakage current is generated in the thin film transistor. Also, because the active layer should be formed thickly in consideration of the over-etching, fabrication time and product cost increase.